Apparatus and methods for synchronizing phase-locked loops

ABSTRACT

Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL&#39;s division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

BACKGROUND

1. Field

Embodiments of the invention relate to electronic systems, and moreparticularly, to synchronization of phase-locked loops (PLLs).

2. Description of the Related Technology

Phase-locked loops (PLLs) can be used in a variety of applications forgenerating an output clock signal having a controlled phase andfrequency relationship to a reference clock signal. PLLs can be used in,for example, telecommunications systems and/or chip-to-chipcommunication.

An integer-N frequency synthesizer can be implemented using a PLL havingan integer frequency divider inserted in the PLL's feedback loop. Theinteger-N frequency synthesizer can be used to synthesize outputfrequencies in steps of a reference frequency by selecting an integerdivision value N of the frequency divider. For example, at steady state,the frequency of the synthesizer's output clock signal should be N timesthe reference clock signal's frequency. Additionally, in an integer-Nfrequency synthesizer, at steady state the output clock signal shouldhave N periods for every period of the reference clock signal.Therefore, a rising edge of the reference clock signal can besynchronized with a rising edge of the output clock signal.

To provide finer steps of output frequency adjustment, a fractional-Nsynthesizer can be used. In contrast to an integer-N frequencysynthesizer that uses integer division values, a fractional-Nsynthesizer permits fractional division values. At steady state, thefrequency of the synthesizer's output clock signal should be N+F/M timesthe reference clock signal's frequency, where N is the integer portionof the division value and F/M is the fractional portion of the divisionvalue.

In certain configurations, an interpolator can be used to generate thefractional portion of the division value. For example, the output of theinterpolator can include a sequence of integer division values with anaverage value given by F/M, where F is the numerator of the fractionalportion and M is the denominator of the fractional portion.

SUMMARY

In one aspect, an apparatus includes a first phase-locked loop (PLL)configured to receive a reference clock signal and to generate an outputclock signal. The first PLL included a programmable divider configuredto receive a division signal, and a ratio of a frequency of the outputclock signal to a frequency of the reference clock signal changes inrelation to the division signal. The apparatus further includes a firstcontrol circuit configured to generate the division signal. The firstcontrol circuit includes an interpolator configured to generate aninterpolated signal based on a fraction numerator signal and based on amodulus signal, and the first control circuit is configured to generatethe division signal based on the interpolated signal. The first controlcircuit further includes a reset phase adjustment calculator configuredto generate a phase adjustment signal and to receive an initializationsignal. The reset phase adjustment calculator includes a counterconfigured to count a number of periods of the reference clock signal,and the counter is configured to be reset by the initialization signal.The phase adjustment signal is based on a count of the counter. Thefirst control circuit further includes a synchronization circuitconfigured to synchronize the first PLL in response to a synchronizationsignal, wherein the synchronization circuit is configured to correct fora synchronization phase error indicated by the phase adjustment signal.

In another aspect, an electronically implemented method of clock signalgeneration is provided. The method includes generating an output clocksignal based on a reference clock signal using a PLL, resetting acounter using an initialization signal, counting a number of periods ofthe reference clock signal using the counter, generating a phaseadjustment signal based on a count of the counter, controlling adivision signal of the PLL using an interpolator, receiving asynchronization signal into a synchronization circuit, synchronizing thePLL in response to a synchronization signal using the synchronizationcircuit, and correcting for a synchronization phase error indicated bythe phase adjustment signal using the synchronization circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of one embodiment of a fractional-Nsynthesizer.

FIG. 2 is a schematic block diagram of one embodiment of a clocksynthesis system including a plurality of fractional-N synthesizers.

FIG. 3 is a schematic block diagram of another embodiment of afractional-N synthesizer.

FIG. 4 is a schematic block diagram of a communications system accordingto one embodiment.

FIG. 5 is a schematic block diagram of another embodiment of afractional-N synthesizer.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description of embodiments presents variousdescriptions of specific embodiments of the invention. However, theinvention can be embodied in a multitude of different ways as definedand covered by the claims. In this description, reference is made to thedrawings where like reference numerals may indicate identical orfunctionally similar elements.

Fractional-N synthesizers can be desirable for use in a wide variety ofelectronic systems because they allow relatively small output frequencysteps over a wide range of reference clock frequencies. However, absentsynchronization, the PLL in a fractional-N synthesizer can lockunpredictably to one of a multitude of possible phases of a referenceclock signal.

In certain electronic systems, it can be desirable to synchronize thephase of a PLL's output clock signal to a known relationship with areference clock signal. For example, in frequency hopping wirelesscommunications systems, a local oscillator may maintain the same phaserelationship with the reference clock signal each time the frequency ofthe local oscillator changes. Furthermore, in multi-PLL systems, it maybe important to maintain the same phase relationship between the outputclock signals of the PLLs.

Provided herein are apparatus and methods for synchronizing PLLs. Incertain implementations, a fractional-N synthesizer includes a PLL and acontrol circuit that controls a division value of the PLL. The controlcircuit can include an interpolator, a reset phase adjustmentcalculator, and a synchronization circuit. The interpolator can be usedto control a fractional portion of the division value based on afraction numerator signal and a fraction denominator or modulus signal.The reset phase adjustment calculator can be used to determine a phaseerror of the PLL associated with synchronizing the PLL during aparticular cycle of the reference clock signal. For example, the resetphase adjustment calculator can include a counter for counting a numberof cycles of the reference clock signal since the fractional-Nsynthesizer was initialized, and the reset phase adjustment calculatorcan generate a phase adjustment signal based on the count. Thesynchronization circuit can synchronize the PLL in response to asynchronization signal, and can correct for a synchronization phaseerror indicated by the phase adjustment signal.

The synchronization circuit can synchronize the PLL and correct for thesynchronization phase error in a variety of ways. For example, incertain implementations, the synchronization circuit can reset theinterpolator to a known state in response to the synchronization signal,and thereafter adjust a state of the interpolator by an amount indicatedby the phase adjustment signal. However, other configurations arepossible. For example, in one implementation, the output clock signal ofthe PLL is provided to a mixer that is in a signal path with a digitalphase rotation circuit, and the synchronization circuit can synchronizethe PLL by adjusting a state of the digital phase rotation circuit by anamount indicated by the phase adjustment signal. In anotherimplementation, the interpolator is implemented using a sigma deltamodulator, and the synchronization phase error is corrected by adjustinga starting value of an integrator of the sigma delta modulator.

The fractional-N synthesizers herein can be synchronized during anyarbitrary period of the reference clock signal. In contrast, certainconventional fractional-N synthesizers can provide limited opportunitiesfor synchronization, such as permitting synchronization only aftermultiple cycles of the reference clock signal. However, such delay maybe unacceptable in certain systems. For example, a fractional-Nsynthesizer using a 1 HZ frequency step may have to wait up to onesecond between available opportunities for synchronization.

The synchronization schemes herein can also be used to synchronizemultiple fractional-N synthesizers such that the output clock signals ofthe synthesizers have a common phase relationship with respect to areference clock signal.

In certain configurations, the fractional-N synthesizer's controlcircuit can also be used to provide a desired phase shift with respectto the reference clock signal. For example, in certain implementations,the reset phase adjustment calculator further includes a phase shiftinput for controlling a phase shift of the PLL's output clock signalrelative to the reference clock signal. For example, the phaseadjustment signal can be based on a sum of a phase shift signalindicating a desired phase shift and a phase error associated withsynchronizing the PLL during a particular reference clock signal period.

Furthermore, in certain implementations, a fractional-N synthesizer canremain synchronized with respect to the reference clock signal evenafter the PLL has been disabled or locked to a different frequency. Forexample, in certain implementations, the counter in the synthesizer'sreset phase adjustment calculator can remain enabled and can continue tocount even when the PLL and/or other circuitry of the fractional-Nsynthesizer is disabled. Subsequently when the PLL is enabled, the resetphase adjustment calculator can be used to generate a phase adjustmentsignal which can be used to synchronize the PLL's output clock signalwith the reference clock signal.

FIG. 1 is a schematic block diagram of one embodiment of a fractional-Nsynthesizer 10. The fractional-N synthesizer 10 includes a PLL 1 and acontrol circuit 2.

The PLL 1 generates an output clock signal CLK_(OUT) and receives areference clock signal CLK_(REF), an enable signal EN, and a divisionsignal DIV. The PLL 1 can divide the output clock signal CLK_(OUT) basedon the division signal DIV to generate a feedback clock signalCLK_(FBK). The PLL 1 can generate an error signal by comparing thefeedback clock signal CLK_(FBK) to the reference clock signal CLK_(REF),and the error signal can be used to control a frequency of the outputclock signal CLK_(OUT).

In the illustrated configuration, the control circuit 2 receives thereference clock signal CLK_(REF), a fraction numerator signal F, afraction denominator or modulus signal M, an integer division signal N,an initialization signal INIT, a synchronization signal SYNC, a phaseshift signal P_(SHIFT), and an enable signal EN. The control circuit 2includes a reset phase adjustment calculator 3, a synchronizationcircuit 4, and a fractional interpolator 5. The reset phase adjustmentcalculator 3 includes a counter 6.

The fractional-N synthesizer 10 can be used to control the frequency ofthe output clock signal CLK_(OUT) to be about N+F/M times the frequencyof the reference clock signal CLK_(REF), where N is the value of theinteger division signal N, F is the value of the fraction numeratorsignal F, and M is the value of the modulus signal M.

The interpolator 5 can be used to generate an interpolated signalcorresponding to a fractional portion of the division signal DIV. Forexample, the interpolated signal can be added to the integer divisionsignal N to generate the division signal DIV. In certainimplementations, the division signal DIV has an integer value whichchanges over time to provide an average division value indicated by thefraction numerator signal F, the modulus signal M, and the integerdivision signal N. For instance, to achieve a division rate of 11.5, thedivision signal DIV can have a value of 11 for one-half of the time anda value of 12 for one-half of the time.

In one embodiment, the interpolator 5 includes a sigma delta modulator.Using a sigma delta modulator for interpolation can reduce or removefrequency sidebands or spurs relative to an interpolator whose outputperiodically alternates between two states. For example, the output ofthe sigma delta modulator can change relatively frequently, therebyshifting noise associated with interpolation to a relatively highfrequency where it can be filtered by the PLL 1.

As shown in FIG. 1, in certain implementations the feedback clock signalCLK_(FBK) can be provided to the control circuit 2 to aid in controllingthe PLL 1. For example, in one implementation, the feedback clock signalCLK_(FBK) clocks at least a portion of the state elements of theinterpolator 5, such that the timing of the interpolator 5 is controlledby the feedback clock signal CLK_(FBK).

The control circuit 2 receives the initialization signal INIT, which canbe used to initialize the control circuit 2 to a known state. In certainimplementations, the initialization signal INIT is used to reset a countof the counter 6, such as to a count value of 0. Thereafter, the counter6 can count a number of cycles of the reference clock signal CLK_(REF)since initialization of the fractional-N synthesizer 10. Additionally,the reset phase adjustment calculator 3 can use the count signalgenerated by the counter 6 to generate a phase adjustment signalindicating a phase error that would be associated with synchronizing thePLL 1 on a particular cycle of the reference clock signal CLK_(REF).

Additionally, as shown in FIG. 1, the control circuit 2 receives thesynchronization signal SYNC. In response to activation of thesynchronization signal SYNC, the synchronization circuit 4 cansynchronize the PLL 1. For example, in certain implementations, thesynchronization circuit 4 can reset the interpolator 5 in response tothe synchronization signal SYNC. Additionally, the synchronizationcircuit 4 can adjust a state of the interpolator 5 by an amountindicated by the phase adjustment signal, thereby correcting the outputphase of the PLL 1 to account for the phase error associated withsynchronizing the PLL 1 during a particular period of the referenceclock signal CLK_(REF).

The illustrated control circuit 2 can be used to synchronize thefractional-N synthesizer's PLL during an arbitrary period of thereference clock signal CLK_(REF). In contrast, certain conventionalfractional-N synthesizers can provide limited opportunities forsynchronization, such as requiring synchronization after multiple cyclesof the reference clock signal CLK_(REF).

In the illustrated configuration, the control circuit 2 receives thephase shift signal P_(SHIFT), which can be used to provide a desiredphase shift between the output clock signal CLK_(OUT) and the referenceclock signal CLK_(REF). In certain configurations, the reset phaseadjustment calculator 3 generates the phase adjustment signal by addingthe phase shift signal P_(SHIFT) to a phase error signal associated withsynchronizing the PLL on a particular cycle. Thus, when thesynchronization circuit 4 resets the interpolator 5, the phase of theoutput clock signal CLK_(OUT) can be adjusted to account for both aphase error associated with synchronization and a phase shift indicatedby the phase shift signal P_(SHIFT).

The fractional-N synthesizer 10 can be configured to maintainsynchronization even when the PLL 1 has been disabled or locked to adifferent frequency. For example, in certain configurations, thefractional-N synthesizer 10 can receive the enable signal EN, which canbe used to disable various circuits of the fractional-N synthesizer,including, for example, portions of the control circuit 2 and/or PLL 1,such as the PLL's oscillator, phase detector, and/or divider. However,in certain implementations, the counter 6 of the reset phase adjustmentcalculator 3 can remain enabled and can continue to count even when thePLL 1 and/or other portions of the control circuit 2 are disabled.Thereafter, the enable signal EN can be asserted, and the reset phaseadjustment calculator 3 can be used to generate a phase adjustmentsignal based on the count of the counter 6. When the synchronizationsignal SYNC is asserted, the synchronization circuit 4 can be used toreset the interpolator 5 and adjust the interpolator's state to accountfor a phase error associated with synchronizing the fractional-Nsynthesizer 10 on a particular cycle of the reference clock signalCLK_(REF).

FIG. 2 is a schematic block diagram of one embodiment of a clocksynthesis system 20 including a plurality of fractional-N synthesizers10 a, 10 b, 10 c.

The first fractional-N synthesizer 10 a includes a first PLL 1 a and afirst control circuit 2 a. Additionally, the second fractional-Nsynthesizer 10 b includes a second PLL 1 b and a second control circuit2 b. Furthermore, the third fractional-N synthesizer 10 c includes athird PLL 1 c and a third control circuit 2 c.

Although the clock synthesis system 20 is illustrated as including threeclock synthesizers, the clock synthesis system 20 can be adapted toinclude more or fewer synthesizers. In certain configurations, thefirst, second and third fractional-N synthesizers 10 a-10 c are disposedon separate integrated circuits (ICs).

In the illustrated configuration, the first, second and thirdfractional-N synthesizers 10 a-10 c each receive the reference clocksignal CLK_(REF), the fraction numerator signal F, the modulus signal M,the integer division signal N, the initialization signal INIT, and thesynchronization signal SYNC. Additionally, the first fractional-Nsynthesizer 10 a has been configured to receive a first phase shiftsignal P_(SHIFT1), the second fractional-N synthesizer 10 b has beenconfigured to receive a second phase shift signal P_(SHIFT2), and thethird fractional-N synthesizer 10 c has been configured to receive athird phase shift signal P_(SHIFT3). Furthermore, the first, second andthird fractional-N synthesizers 10 a-10 c have been configured togenerate different output clock signals. For example, the firstfractional-N synthesizer 10 a generates a first output clock signalCLK_(OUT1), the second fractional-N synthesizer 10 b generates a secondoutput clock signal CLK_(OUT2), and the third fractional-N synthesizer10 c generates a third output clock signal CLK_(OUT3).

Even when the phase shift signals P_(SHIFT1)-P_(SHIFT3) have the samevalue, absent synchronization, the first, second, and third fractional-Nsynthesizers 10 a-10 c can have output clock signals locked to differentphases of the reference clock signal CLK_(REF).

The illustrated configuration can be used to synchronize the first,second, and third fractional-N synthesizers 10 a-10 c to a common outputphase with respect to the reference clock signal CLK_(REF).

For example, the first, second and third fractional-N synthesizers 10a-10 c each receive the initialization signal INIT. In a manner similarto that described earlier with respect to FIG. 1, the initializationsignal INIT can be used to initialize or reset an initial state ofcounters associated with the synthesizers' reset phase adjustmentcalculators.

Thereafter, when the synchronization signal SYNC is asserted, the outputphase of the PLLs 1 a-1 c can be corrected based on the count values toaccount for a phase error associated with synchronizing the synthesizerson a particular reference clock cycle. In certain implementations, thesynchronization signal can be applied to the fractional-N synthesizers10 a-10 c at different times, such as during different cycles of thereference clock signal CLK_(REF). After the PLLs 1 a-1 c have beensynchronized using the control circuits 2 a-2 c, respectively, the PLLs1 a-1 c can have about the same output phase relative to one anotherwhen the phase shift signals P_(SHIFT1)-P_(SHIFT3) have the same value.For example, the control circuits 2 a-2 c can include counters that canbe reset to a known value during initialization, and thereafter thestate of the interpolators can be adjusted based on a count of thecontrol circuit's counters.

Additional details of the fractional-N synthesizers 10 a-10 c can be asdescribed earlier.

Although FIG. 2 illustrates one configuration of a clock synthesissystem including multiple fractional-N synthesizers, otherconfigurations are possible. For example, in certain implementations,portions of the control circuits 2 a-2 c can be shared amongst thesynthesizers. Furthermore, in certain implementations, the synthesizerscan receive separate control signals, including, for example, separatesynchronization signals and/or enable signals. Furthermore, althoughFIG. 2 shows a configuration in which the first, second, and thirdfractional-N synthesizers 10 a-10 c receive different phase shiftsignals, the teachings herein are applicable to configuration in whichthe fractional-N synthesizers receive the same phase signal orconfigurations in which phase shift signals are omitted.

FIG. 3 is a schematic block diagram of one embodiment of a fractional-Nsynthesizer 40. The fractional-N synthesizer 40 includes a PLL 41 and acontrol circuit 42. The fractional-N synthesizer 40 generates the outputclock signal CLK_(OUT) and receives the reference clock signalCLK_(REF), the fraction numerator signal F, the modulus signal M, theinteger division signal N, the initialization signal INIT, the phaseshift signal P_(SHIFT), and the synchronization signal SYNC.

The PLL 41 includes a phase detector 43, a loop filter 45, a voltagecontrolled oscillator 46, and a programmable divider 47. The phasedetector 43 includes a first input for receiving the reference clocksignal CLK_(REF) and a second input for receiving a feedback clocksignal CLK_(FBK). The phase detector 43 further includes an outputelectrically connected to an input of the loop filter 45. The loopfilter 45 includes an output electrically connected to an input of theVCO 46. The VCO 46 further includes an output for generating the outputclock signal CLK_(OUT). The programmable divider 47 includes an inputfor receiving the output clock signal CLK_(OUT), an output forgenerating the feedback clock signal CLK_(FBK), and a control input forreceiving a division signal DIV from the control circuit 42.

The phase detector 43 can include circuitry configured to generate anerror signal based on a phase difference and/or frequency differencebetween the reference clock signal CLK_(REF) and the feedback clocksignal CLK_(FBK). Additionally, the phase detector 43 can include chargepump circuitry that can control a flow of current into or out of theinput of the loop filter 45 based on the error signal. Although oneexample implementation of the phase detector 43 has been described, thephase detector 43 can be implemented using a variety of configurations.

The loop filter 45 can be any suitable PLL loop filter, including forexample, an active loop filter or a passive loop filter. The loop filter45 can be used for a variety of purposes, such as to maintain thestability of the PLL 41.

The VCO 46 can be implemented using a variety of oscillatorconfigurations, including, for example, an inductor-capacitor (LC) tankoscillator implementation or a rotary travelling wave oscillator (RTWO)implementation. For example, an RTWO is described in U.S. Pat. No.6,556,089, which is incorporated by reference herein. Although twoexamples of VCOs have been provided, other configurations can be used.

The programmable divider 47 receives the division signal DIV, and candivide the output clock signal CLK_(OUT) by a division rate indicated bythe division signal DIV to generate the feedback clock signal CLK_(FBK).In certain implementations, the programmable divider 47 is an integerdivider, and the division signal DIV has an integer value that changesover time to achieve the desired fractional division rate.

Although FIG. 3 illustrates one configuration of a PLL, the teachingsherein are applicable to other PLL implementations. For example, the PLL41 can be adapted to include additional structures, such as additionaldividers, filters and/or other circuitry.

The control circuit 42 includes a reset phase adjustment calculator orcalculation circuit 51, an interpolator 52, a synchronization circuit53, a multiplexer 54, a first adder 61, and a second adder 62. The resetphase adjustment calculation circuit 51 includes a third adder 63, amodulo-M counter 64, and a multiplier 65.

The modulo-M counter 64 includes a clock input for receiving thereference clock signal CLK_(REF), a reset input for receiving theinitialization signal INIT, and an output for generating a count valuek. The multiplier 65 includes a first input for receiving the countvalue k, a second input for receiving the fraction numerator signal F,and an output for generating a multiplied signal kF. The third adder 63includes a first input for receiving a phase shift signal P_(SHIFT), asecond input for receiving the multiplied signal kF, and an output forgenerating a phase adjustment signal P, which can have a valueP_(SHIFT)+kF corresponding to a sum of the phase shift signal P_(SHIFT)and the multiplied signal kF.

The second adder 62 includes a first input for receiving the phaseadjustment signal P, a second input for receiving the fraction numeratorsignal F, and an output for generating an adjusted fraction numeratorsignal P+F, which can have a value corresponding to a sum of the phaseadjustment signal P and the fraction numerator signal F. The multiplexer54 includes a first input for receiving the adjusted fraction numeratorsignal P+F, a second input for receiving the fraction numerator signalF, a selection control input for receiving a selection control signalSEL, and an output for generating a selected signal. The synchronizationcircuit 53 includes a first clock input for receiving the referenceclock signal CLK_(REF), a second clock input for receiving the feedbackclock signal CLK_(FBK), a synchronization input for receiving thesynchronization signal SYNC, a first output for generating the selectioncontrol signal SEL, and a second output for generating a reset signalRESET.

The interpolator 52 includes a fractional input for receiving theselected signal from the multiplexer 54, a modulus input for receivingthe modulus signal M, a clock input for receiving the feedback clockCLK_(FBK), a reset input for receiving the reset signal RESET, and anoutput for generating an interpolated signal corresponding to afractional portion of the PLL's divisional signal DIV. In certainimplementations, the interpolated signal generated by the interpolator52 is an integer, but has an average value determined by the ratio ofthe signals received at the interpolator's fraction numerator input andmodulus input. In one embodiment, the interpolator includes a sigmadelta modulator.

The first adder 61 includes a first input for receiving the interpolatedsignal from the interpolator 52, a second input for receiving theinteger division signal N, and an output for generating the PLL'sdivision signal DIV.

The illustrated control circuit 42 can be used to generate a divisionsignal DIV for the PLL 41. Additionally, the control circuit 42 receivesa synchronization signal SYNC that can synchronize the phase of theoutput clock signal CLK_(OUT) to a known relationship with the referenceclock signal CLK_(REF). In one embodiment, the control circuit 42 cancontrol the output clock signal CLK_(OUT) to have a phase differencewith the reference clock signal CLK_(REF) that is about equal to theknown phase relationship plus the phase shift signal P_(SHIFT).

As will be described in detail below, the control circuit 42 permitssynchronization during any cycle of the reference clock signalCLK_(REF). In contrast, certain conventional synchronization circuitsprovide limited opportunities for synchronization, such as requiringsynchronization after a certain number of cycles of the reference clocksignal CLK_(REF).

During normal operation of the fractional-N synthesizer 40 when thefractional-N synthesizer 40 is not being synchronized, the select signalSEL can control the multiplexer 54 such that the interpolator 52receives the fraction numerator signal F as an input. Thus, theinterpolator 52 can generate the interpolated signal based on aninterpolation of the fraction numerator signal F and the modulus signalM.

However, in response to activation of the synchronization signal SYNC,the synchronization circuit 53 can reset the interpolator 52 to a knownstate. Additionally, the synchronization circuit 53 can use the selectsignal SEL to control the multiplexer 54 to provide the adjustedfraction numerator signal P+F to the interpolator 52. Configuring thesynchronization circuit 53 in this manner can operate to set the phaseof the PLL 41 to a known value and to adjust for a synchronization phaseerror associated with synchronizing the PLL 41 in a particular cycle ofthe reference clock signal CLK_(REF). Thus, the synchronization circuit53 can provide phase adjustment to permit the PLL 41 to be synchronizedduring any period of the reference clock signal CLK_(REF).

Although the illustrated configuration provides phase adjustment byproviding the adjusted fractional numerator signal P+F to theinterpolator 52 for a single clock cycle, other configurations arepossible. For example, in one embodiment, a phase adjustment of P/j+F isprovided to the interpolator 52 for j periods of the reference clocksignal CLK_(REF). Configuring a control circuit to provide phaseadjustment in this manner can increase phase adjustment resolution by afactor of j. In another embodiment, phase adjustment is provided using aphase adjustment signal having two or more different values acrossmultiple clock cycles, and the amount of phase adjustment is based on asum of the phase adjustment signal values.

In the illustrated configuration, the synchronization circuit 53receives the feedback clock signal CLK_(FBK). In certainimplementations, the synchronization circuit 53 can use the feedbackclock signal CLK_(FBK) to re-time select signal SEL and/or the resetsignal RESET. However, other configurations are possible.

The fractional-N synthesizer 40 can be used to control the frequency ofthe output clock signal CLK_(OUT) based on the frequency of thereference clock signal CLK_(REF). For example, the output frequencyf_(out) of the output clock signal CLK_(OUT) can be given by Equation 1below, where f_(ref) is the frequency of the reference clock signalCLK_(OUT), M is the value of the modulus signal M, N is the value of theinteger division signal N, and F is the value of the fraction numeratorsignal F.f _(out) =f _(ref)(N+F/M)  Equation 1

Since N, F, and M are integers, the phase of the output clock signalCLK_(OUT) can align with one out of X edges of the reference clockCLK_(REF), where X is the least common multiple of F and M. Absentsynchronization, the output clock signal CLK_(OUT) can lock to thereference clock signal CLK_(REF) in multiple different ways.

When the reference clock signal CLK_(REF) is sinusoidal, the normalizedvoltage of the reference clock signal CLK_(REF) versus time can be givenby Equation 2 below, where π is the mathematic constant pi and whereφ_(ref) is the phase of the reference clock signal CLK_(REF).V _(ref)(t)=cos(2πf _(ref) t+φ _(ref))  Equation 2

Additionally, when the fractional interpolator is reset at time t=0, theoutput clock signal CLK_(OUT) of the PLL 41 can have a phase φ_(rel)relative to the reference clock signal CLK_(REF). If the interpolator 52is reset at an arbitrary time t_(reset), the normalized voltage of theoutput clock signal CLK_(OUT) can be given by Equation 3 below.V _(out)(t)=cos(2πf _(out)(t−t _(reset))+φ_(ref)+φ_(rel))  Equation 3

When the reset time t_(reset) is limited to an integer number of periodsof the reference clock signal CLK_(REF), then t_(reset) can be equal toK/f_(ref), where K is an integer. Thus the normalized voltage of theoutput clock signal CLK_(OUT) can be given by Equation 4 below, wherethe desired output phase φ_(desired)=φ_(ref)+φ_(rel).

$\begin{matrix}{{V_{out}(t)} = {\cos\left( {{2\pi\;{f_{out}\left( {t - \frac{K}{f_{ref}}} \right)}} + \varphi_{desired}} \right)}} & {{Equation}\mspace{14mu} 4}\end{matrix}$

Substituting Equation 1 into Equation 4 and rearranging terms yieldsEquation 5 below.

$\begin{matrix}{{V_{out}(t)} = {\cos\left( {{2\pi\;{f_{ref}\left( {N + \frac{F}{M}} \right)}} + {{- 2}\;\pi\;{K\left( {N + \frac{F}{M}} \right)}} + \varphi_{desired}} \right)}} & {{Equation}\mspace{14mu} 5}\end{matrix}$

Since a sinusoid can be represented by cos(2π*f*t+φ), the output phaseof the output clock signal CLK_(OUT) can be given by Equation 6 below.

$\begin{matrix}{{{Output}\mspace{14mu}{Phase}} = {{{- 2}\pi\;{K\left( {N + \frac{F}{M}} \right)}} + \varphi_{desired}}} & {{Equation}\mspace{14mu} 6}\end{matrix}$

Since adding an integer multiple of 2π does not change the phase of asinusoidal signal, and since K, F, M, and N are integers, Equation 6 canbe reduced to Equation 7 below.

$\begin{matrix}{{{Output}\mspace{14mu}{Phase}} = {{{- 2}\pi\; K\frac{F}{M}} + \varphi_{desired}}} & {{Equation}\mspace{14mu} 7}\end{matrix}$

When KF/M is an integer, the output clock signal CLK_(OUT) can have thedesired phase φ_(desired) and an opportunity for synchronizing theoutput clock signal CLK_(OUT) to the reference clock signal CLK_(REF)can be present. In general, this condition can occur only every K=n*Mperiods of the reference clock signal CLK_(REF), where n is an integer.Thus, permitting resets only when this condition is true can limitopportunities for synchronizing the PLL 41 to only about everyn*M/f_(ref) seconds. For instance, in a fractional-N PLL where theoutput clock CLK_(OUT) has a frequency that can be controlled in stepsof about 1 Hz, opportunities to synchronize the PLL 41 can be separatedby as long as about one second.

The reset phase adjustment calculation circuit 51 can be used to permitsynchronization of the PLL 41 during any period of the reference clocksignal CLK_(REF). For example, when K is not equal to n*M, the value ofK can be given by Equation 8 below, where k is an integer.K=nM+k  Equation 8

Thus, by substituting Equation 8 into Equation 6 above and removinginteger multiples of 2π, the output phase of the output clock signalCLK_(OUT) in this condition can be given by Equation 9 below.

$\begin{matrix}{{{Output}\mspace{14mu}{Phase}} = {{{- 2}\pi\frac{k\; F}{M}} + \varphi_{desired}}} & {{Equation}\mspace{14mu} 9}\end{matrix}$

The phase error due to synchronizing during a reference period where kis not equal to zero is then given by Equation 10 below.

$\begin{matrix}{{\Delta\;\varphi} = {{- 2}\pi\; k\frac{F}{M}}} & {{Equation}\mspace{14mu} 10}\end{matrix}$

The illustrated control circuit 42 permits synchronization of the PLL 41during any period of the reference clock signal CLK_(REF) by keepingcount of the number of periods of the reference clock signal CLK_(REF)since the fractional-N synthesizer 40 was initialized. Additionally,when synchronization occurs, the control circuit 42 corrects for thephase error associated with synchronizing during an arbitrary period ofthe reference clock signal CLK_(REF).

For example, when the PLL 41 is being synchronized, the synchronizationcircuit 53 can reset the interpolator 52 to a known state. Thereafter,the fraction numerator input of the interpolator 52 is switched from thefraction numerator signal F to the adjusted fraction numerator signalP+F for a cycle of the reference clock signal CLK_(REF). Configuring theinterpolator 52 in this manner increments the phase of the PLL 41 byabout 2π*P/M radians. In certain implementations, the synchronizationcircuit 53 provides the adjusted fraction numerator signal P+F to theinterpolator 52 one clock cycle after resetting the interpolator 52 to aknown state. However, other configurations are possible. For example, inone implementation, the adjusted fraction numerator signal P+F isprovided to the interpolator 52 two or more clock cycles after resettingthe interpolator 52. Configuring the synchronization circuit 53 in thismanner can permit pipelining of the phase adjustment calculation by thereset phase adjustment calculation circuit 51, which may increase amaximum frequency of the reference clock signal CLK_(REF) that thefractional-N synthesizer 40 can support.

To account for the phase error Δφ given in Equation 10, the reset phaseadjustment calculation circuit 51 can generate a phase adjustment equalto about −kF. Furthermore, to provide an additional phase shift oradjustment φ_(shift) in radians, the reset phase adjustment calculationcircuit 51 can generate the phase adjustment signal P to have a valuegiven by Equation 11 below.

$\begin{matrix}{P = {{kF} + {M\frac{\varphi_{shift}}{2\;\pi}}}} & {{Equation}\mspace{14mu} 11}\end{matrix}$

As shown in FIG. 3, the modulo-M counter 64 can be used to count anumber of reference periods of the reference clock signal CLK_(REF)since the fractional-N synthesizer 40 was initialized using theinitialization signal INIT. Additionally, the modulo-M counter 64 canoutput the count signal k as a result. The multiplier 65 can be used tomultiply the count signal k by the fraction numerator signal F togenerate the multiplied signal kF. Furthermore, the third adder 63 canbe used to add the multiplied signal kF and the phase shift signalP_(SHIFT) to generate the phase adjustment signal P. In certainconfigurations, the phase shift signal P_(SHIFT) can have a value equalto about M*φ_(shift)/2π, where φ_(shift) corresponds to any additionalphase shift in radians.

To initialize the fractional-N synthesizer 40, the initialization signalINIT can be asserted. The initialization signal INIT can reset a countof the modulo-M counter 64. After initialization, the modulo-M counter64 can count a number of periods of the reference clock signal CLK_(REF)to generate the count signal k, which can be used to generate the phaseadjustment signal P.

Later, during an arbitrary period of the reference clock signalCLK_(REF), the synchronization signal SYNC can be asserted. Thesynchronization circuit 53 can use the synchronization signal SYNC toreset the interpolator 52. Thereafter, the synchronization circuit 53can control the multiplexer 54 using the select signal SEL so that themultiplexer 54 passes the adjusted fraction numerator signal P+F to theinterpolator's fractional input for one period, or by using otherconfigurations, such as providing a phase adjustment of P/j+F for jperiods. The phase of the output clock signal CLK_(OUT) will then besynchronized to the reference clock signal CLK_(REF) with any phaseshift indicated by the phase shift signal P_(SHIFT).

When multiple PLLs are synchronized, all of the PLLs can be initializedduring the same period of the reference clock signal CLK_(REF).Thereafter, the PLLs can be synchronized using a synchronization signalon the same or different periods of reference clock signal CLK_(REF).After synchronization, the PLLs can have consistently the same phaserelationship with the reference clock signal CLK_(REF).

Although FIG. 3 illustrates one example implementation of a controlcircuit including a reset phase adjustment circuit, other configurationsare possible.

In the illustrated configuration, the reference clock signal CLK_(REF)is provided to the PLL 41 without division. However, in otherconfigurations, a reference clock divider is used to divide thereference clock signal before it is provided to the PLL 41. In such aconfiguration, an amount that the count of the modulo-M counter 64 isincremented per cycle of the reference clock signal CLK_(REF) can bebased on a division rate of the reference clock divider. For example,when a division rate of the reference clock divider changes, anincrement value of the modulo-M counter can be changed based on thereference clock divider's division rate.

FIG. 4 is a schematic block diagram of a communications system 100according to one embodiment.

The communications system 100 includes the PLL 41, the interpolator 52,the adder 61, the synchronization circuit 53, and the reset phaseadjustment calculation circuit 51, which can be as described earlier.The communications system 100 further includes a state element 81, atransceiver 82, a duplexer 83, and an antenna 84.

The transceiver 82 includes a first digital phase rotation circuit 91, asecond digital phase rotation circuit 92, an analog-to-digital converter(ADC) 93, a digital-to-analog converter (DAC) 94, a receive filter 95, atransmit filter 96, a first mixer 97, a second mixer 98.

The second digital phase rotation circuit 92 includes a data input thatreceives transmit data, a control input electrically connected to a dataoutput of the state element 81, and a data output electrically connectedto an input of the DAC 94. The transmit filter 96 includes an inputelectrically connected to an output of the DAC 94 and an outputelectrically connected to a signal input of the second mixer 98. Thesecond mixer 98 further includes a clock input configured to receive theoutput clock signal CLK_(OUT) and an output electrically connected to atransmit terminal of the duplexer 83. The duplexer 83 further includesan antenna terminal electrically connected to the antenna 84 and areceive terminal electrically connected to a signal input of the firstmixer 97. The first mixer 97 further includes a clock input configuredto receive the output clock signal CLK_(OUT) and an output electricallyconnected to an input of the receive filter 95. The ADC 93 includes aninput electrically connected to an output of the receive filter 95 andan output electrically connected to a data input of the first digitalphase rotation circuit 91. The first digital phase rotation circuit 91further includes a control input electrically connected to the dataoutput of the state element 81 and a data output configured to generatereceive data. The state element 81 further includes a data inputconfigured to receive the phase adjustment signal P from the reset phaseadjustment calculation circuit 51 and an enable input electricallyconnected to an output of the synchronization circuit 53.

In the illustrated communications system 100, the output clock signalCLK_(OUT) generated by the PLL 41 has been used as a clock signal forupconverting data for transmission via the antenna 84 and fordownconverting data received from the antenna 84.

The communications system 100 can have a total receive phase based on acombination of the phase of the receive data path and the phase of theoutput clock signal CLK_(OUT). Additionally, the communications system100 can have a total transmit phase based on a combination of the phaseof the transmit data phase and the phase of the output clock signalCLK_(OUT).

The illustrated communications system 100 can be synchronized during anyperiod of the reference clock signal CLK_(REF). However, in contrast tothe fractional-N synthesizer of FIG. 3, the illustrated communicationssystem 100 includes a different scheme for correcting for a phase errorassociated with synchronizing the PLL 41 during a particular referenceperiod. For example, as shown in FIG. 4, the phase adjustment signal Pis provided as in input to the state element 81. When thesynchronization signal SYNC is asserted, the synchronization circuit 53can reset the interpolator 52. Additionally, the synchronization circuit53 can load the state element 81 with the phase adjustment signal P. Forexample, in one implementation, the state element 81 includes aplurality of latches and/or flip-flops configured to load the phaseadjustment signal P in response to the synchronization circuit 53. Thestate element 81 can provide the stored phase adjustment signal P to thefirst and second digital phase rotation circuits 91, 92.

Thus, the illustrated configuration corrects for synchronization phaseerror by correcting a phase of the transmit signal path and/or receivesignal path.

Although FIG. 4 illustrates one configuration of a communications system100 in accordance with the teachings herein, other implementations arepossible. For example, the transceiver 82 can include more or fewercomponents in the transmit path and/or receive path, or componentsarranged in a different implementation. For instance, the illustratedcommunication system 100 is implemented using an intermediate frequencysampled (IF-sampled) transceiver configuration, but the teachings hereinare applicable to superheterodyne systems and zero intermediatefrequency (zero-IF) systems.

FIG. 5 is a schematic block diagram of one embodiment of a fractional-Nsynthesizer 130. The fractional-N synthesizer includes the PLL 41 and acontrol circuit 112. The control circuit 112 includes the reset phaseadjustment calculation circuit 51, the first adder 61, thesynchronization circuit 53, and a sigma delta modulator (SDM)interpolator 122.

The fractional-N synthesizer 130 of FIG. 5 is similar to thefractional-N synthesizer 40 of FIG. 3, except that the fractional-Nsynthesizer 130 includes the control circuit 112, which is implementedin a different configuration than the control circuit 42 of FIG. 3. Forexample, relative to the control circuit 42 of FIG. 3, the controlcircuit 112 of FIG. 5 omits the second adder 62 and the multiplexer 54,and includes the SDM interpolator 122 rather than the fractionalinterpolator 52.

As shown in FIG. 5, the SDM interpolator 122 includes a fractionnumerator input that receives the fraction numerator signal F, a modulusinput that receives the modulus signal M, a reset input that receives areset signal from the synchronization circuit 53, a clock input thatreceives the feedback clock signal CLK_(FBK), a seed input that receivesthe phase adjustment signal P, and an output that generates aninterpolated signal for the first adder 61.

In response to activation of the synchronization signal SYNC, thesynchronization circuit 53 can reset the SDM interpolator 122.Thereafter, the SDM interpolator 122 can be loaded with an integrationseed or starting value corresponding to a default seed value plus thevalue of the phase adjustment signal P at the time of interpolatorreset, or a constant number of periods after reset. Thus, in theillustrated configuration, the synchronization circuit 53 cansynchronize the PLL 41 by adjusting an integration starting value of theSDM interpolator 122 by an amount indicated by the phase adjustmentsignal P.

Applications

Devices employing the above described schemes can be implemented intovarious electronic devices. Examples of the electronic devices caninclude, but are not limited to, consumer electronic products, parts ofthe consumer electronic products, electronic test equipment, etc.Examples of the electronic devices can also include circuits of opticalnetworks or other communication networks. The consumer electronicproducts can include, but are not limited to, an automobile, acamcorder, a camera, a digital camera, a portable memory chip, a washer,a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, amulti-functional peripheral device, etc. Further, the electronic devicecan include unfinished products, including those for industrial, medicaland automotive applications.

The foregoing description and claims may refer to elements or featuresas being “connected” or “coupled” together. As used herein, unlessexpressly stated otherwise, “connected” means that one element/featureis directly or indirectly connected to another element/feature, and notnecessarily mechanically. Likewise, unless expressly stated otherwise,“coupled” means that one element/feature is directly or indirectlycoupled to another element/feature, and not necessarily mechanically.Thus, although the various schematics shown in the figures depictexample arrangements of elements and components, additional interveningelements, devices, features, or components may be present in an actualembodiment (assuming that the functionality of the depicted circuits isnot adversely affected).

Although this invention has been described in terms of certainembodiments, other embodiments that are apparent to those of ordinaryskill in the art, including embodiments that do not provide all of thefeatures and advantages set forth herein, are also within the scope ofthis invention. Moreover, the various embodiments described above can becombined to provide further embodiments. In addition, certain featuresshown in the context of one embodiment can be incorporated into otherembodiments as well. Accordingly, the scope of the present invention isdefined only by reference to the appended claims.

What is claimed is:
 1. An apparatus comprising: a first phase-lockedloop (PLL) configured to receive a reference clock signal and togenerate an output clock signal, wherein the first PLL comprises aprogrammable divider configured to receive a division signal, wherein aratio of a frequency of the output clock signal to a frequency of thereference clock signal changes in relation to the division signal; afirst control circuit configured to generate the division signal,wherein the first control circuit comprises: an interpolator configuredto generate an interpolated signal based on a fraction numerator signaland based on a modulus signal, wherein the first control circuit isconfigured to generate the division signal based on the interpolatedsignal; a reset phase adjustment calculator configured to generate aphase adjustment signal and to receive an initialization signal, whereinthe reset phase adjustment calculator comprises a counter configured tocount a number of periods of the reference clock signal, wherein thecounter is configured to be reset by the initialization signal, andwherein the phase adjustment signal is based on a count of the counter;and a synchronization circuit configured to synchronize the first PLL inresponse to a synchronization signal, wherein the synchronizationcircuit is configured to correct for a synchronization phase errorindicated by the phase adjustment signal.
 2. The apparatus of claim 1,wherein the synchronization circuit is configured to correct for thesynchronization phase error by adjusting a state of the interpolator byan amount indicated by the phase adjustment signal.
 3. The apparatus ofclaim 2, wherein the synchronization circuit is further configured toreset the interpolator before adjusting the state of the interpolator.4. The apparatus of claim 2, wherein the synchronization circuit adjuststhe state of the interpolator to correct for the synchronization phaseerror in a single cycle of the reference clock signal.
 5. The apparatusof claim 2, wherein the synchronization circuit adjusts the state of theinterpolator to correct for the synchronization phase error overmultiple cycles of the reference clock signal.
 6. The apparatus of claim1, further comprising a second PLL and a second control circuitconfigured to generate a division signal of the second PLL, wherein thesecond control circuit comprises a synchronization circuit and a resetphase adjustment calculator comprising a counter, wherein theinitialization signal is configured to reset a count of the counter ofthe second control circuit.
 7. The apparatus of claim 6, wherein thesecond control circuit is configured to synchronize the second PLL inresponse to the synchronization signal, and wherein an output clocksignal of the second PLL and the output clock signal of the first PLLhave about the same phase after synchronization.
 8. The apparatus ofclaim 1, wherein the reset phase adjustment calculator further comprisesa multiplier configured to generate a multiplied signal by multiplyingthe fraction numerator signal by the count of the counter.
 9. Theapparatus of claim 8, wherein the reset phase adjustment calculatorfurther comprises an adder configured to generate the phase adjustmentsignal by adding the multiplied signal and a phase shift signal.
 10. Theapparatus of claim 9, wherein the first control circuit furthercomprises: a multiplexer including an output, a first input configuredto receive the phase adjustment signal, a second input configured toreceive the fraction numerator signal, and a selection control inputconfigured to receive a selection control signal from thesynchronization circuit, wherein the interpolator includes a fractionnumerator input electrically connected to an output of the multiplexerand a modulus input configured to receive the modulus signal.
 11. Theapparatus of claim 1, wherein the interpolator comprises a sigma deltamodulator, and wherein the synchronization circuit is configured tocorrect for the synchronization phase error by adjusting an integrationstarting value of the sigma delta modulator by an amount indicated bythe phase adjustment signal.
 12. The apparatus of claim 1, furthercomprising a transceiver comprising a digital phase rotation circuit anda mixer disposed in a signal path, wherein the mixer includes a clockinput configured to receive the first output clock signal, wherein thesynchronization circuit is configured to correct for the synchronizationphase error by adjusting a state of the digital phase rotation circuitby an amount indicated by the phase adjustment signal.
 13. The apparatusof claim 12, wherein the signal path comprises a receive path, whereinthe transceiver further comprises: a receive filter including an inputand an output, wherein the input of the receive filter is electricallyconnected to an output of the mixer; and an analog-to-digital converterincluding an input electrically connected to the output of the receivefilter and an output electrically connected to a data input of thedigital phase rotation circuit.
 14. The apparatus of claim 12, whereinthe signal path comprises a transmit path, wherein the transceiverfurther comprises: a digital-to-analog converter including an inputelectrically connected to a data output of the digital phase rotationcircuit and an output; and a transmit filter including an inputelectrically connected to the output of the digital-to-analog converterand an output electrically connected to a data input of the mixer. 15.The apparatus of claim 12, wherein the first control circuit furthercomprises a state element having a data input configured to receive thephase adjustment signal and a data output electrically connected to acontrol input of the digital phase rotation circuit, wherein thesynchronization circuit is configured to load the state element with thephase adjustment signal in response to the synchronization signal. 16.An electronically-implemented method of clock signal generation, themethod comprising: generating an output clock signal based on areference clock signal using a phase-locked loop (PLL); resetting acounter using an initialization signal; counting a number of periods ofthe reference clock signal using the counter; generating a phaseadjustment signal based on a count of the counter; controlling adivision signal of the PLL using an interpolator; receiving asynchronization signal into a synchronization circuit; synchronizing thePLL in response to a synchronization signal using the synchronizationcircuit; and correcting for a synchronization phase error indicated bythe phase adjustment signal using the synchronization circuit.
 17. Themethod of claim 16, wherein synchronizing the PLL comprises adjusting astate of the interpolator by an amount indicated by the phase adjustmentsignal.
 18. The method of claim 17, further comprising resetting theinterpolator before adjusting the state of the interpolator.
 19. Themethod of claim 16, wherein synchronizing the PLL comprises adjusting astate of the digital phase rotation circuit by an amount indicated bythe phase adjustment signal.
 20. The method of claim 19, furthercomprising: rotating a phase of a digital receive signal using thedigital phase rotation circuit.
 21. The method of claim 19, furthercomprising: rotating a phase of a digital transmit signal using thedigital phase rotation circuit.
 22. The method of claim 19, whereinsynchronizing the PLL comprises adjusting an integration starting valueof a sigma delta modulator of the interpolator by an amount indicated bythe phase adjustment signal.